1. Field of the Invention
The present invention relates to a multiport semiconductor static memory or static random access memory (hereinafter abbreviated as xe2x80x9cSRAMxe2x80x9d) having multiple input/output terminals for data. More particularly, the present invention relates to a dual-port (2 port) SRAM with ports each exclusive to a read or write operation.
2. Related Background Art
With the development of multimedia equipment, a demand for faster semiconductor devices, especially for faster SRAMs, grows with each passing year. Among various semiconductor memories, the SRAMs are particularly suited for speeding up. Therefore the demand for them is on the increase.
The SRAMs, in general, are classified into a single port type having a single input/output port for data and a multiport type having multiple ports. The multiport SRAMs are used particularly for the purpose of realizing a high transfer rate. Among the multiport SRAMs, dual-port SRAMs having two ports are used often. Since the dual-port SRAMs allow the two ports to operate simultaneously, the dual-port SRAMs are suited for speeding up because twice the transfer rate can be realized during operation compared with a case where a single port SRAM alone is operated. Among the dual-port SRAMs, a 1-Read and 1-Write type configuration is used often, where the function of each port is limited to a write operation or a read operation.
FIG. 8 shows a configuration of a memory cell in an 8-transistor (8 Tr) type dual-port SRAM. One memory cell is configured with eight transistors in total including: two CMOS inverters, each made up of one PMOS transistor and one NMOS transistor; and four access transistors. Such an 8 Tr type is the most commonly used memory cell among the dual-port SRAM memory cells because its cell area can be made small due to the configuration including four access transistors. Note here that the configuration of the inverter is not limited to the CMOS type.
In FIG. 8, memory cells 1a and 1b are each made up of two inverters 4 connected like a ring and constituting a latch functioning as a storage unit in a memory circuit; a pair of write access transistors (NMOS) 2; and a pair of read access transistors (NMOS) 3.
WWL denotes a write word line, RWL denotes a read word line, WBL1 and WBL2 denote a write bit line (positive), /WBL1 and /WBL2 denote a write bit line (negative), RBL1 and RBL2 denote a read bit line (positive) and /RBL1 and /RBL2 denote a read bit line (negative).
SA1 and SA2 are sense amplifiers for amplifying potential differences between the read bit lines RBL1 and /RBL1 and between the read bit lines RBL2 and /RBL2, respectively.
1a and 1b are adjacent memory cells arranged in a row (i.e., in the direction along word lines), which are connected to different bit lines along the column direction (i.e., the direction along bit lines) but are connected to the common read/write word lines in the row direction (i.e., the direction along the word lines WWL and RWL).
Note here that substrate potentials of the access transistors 2 and 3 equal the ground potential VSS unless otherwise specified, and their description in the drawings will be omitted.
An access time of SRAMs is a time period from the input of a control signal from outside to the reading out of the stored data to the outside. In this access time, the reading out of data from memory cells actually is the most time-consuming operation. As for the memory cell 1b conducting the reading operation, a time duration required for activating the read word line RWL and charging the bit lines (RBL2 and /RBL2) with data from the memory cells (data to be read out) occupies a considerable portion of the access time. This is because it takes much time to charge a bit line, which is a relatively long line (i.e., having large load resistance and load capacitance), with the memory cell made up of small transistors, i.e., having a small current-carrying capability. The potential (RD and /RD) output to the bit lines are amplified by a sense amplifier (hereinafter abbreviated as xe2x80x9cSAxe2x80x9d) in the latter stage and then are output to the outside. In this amplifying operation, an error might occur during a reading-out process due to the influence of an offset of the SA, noise on the bit lines and the like. In order to avoid this error, a larger potential is desired for the bit lines when amplifying by means of SAs, and therefore a time duration for obtaining such a large potential is required.
In the case of the dual-port SRAM, however, a problem would occur when adjacent memory cells arranged in a row are accessed through the two ports simultaneously. For instance, as shown in FIG. 8, the memory cell 1a and the memory cell 1b respectively might conduct a writing operation and a reading operation simultaneously. In this case, in order to enable the memory cell 1a to conduct the writing operation, the write word line WWL is activated. Additionally, in order to enable the memory cell 1b to conduct the reading operation, the read word line RWL is activated. However, since both of these word lines WWL and RWL are connected commonly to the memory cells 1a and 1b, these word lines are activated simultaneously for the memory cells 1a and 1b. 
A particular problem in this case concerns the read bit lines RBL2 and /RBL2 in the memory cell 1b, which conducts a reading operation. For the inverter latch 4, not only the read bit lines RBL2 and /RBL2 but also the write bit lines WBL2 and /WBL2 function as loads through the two pairs of access transistors, and therefore the load capacitance of the bit lines to be driven becomes twice, which results in the delay in driving the read bit lines RBL2 and /RBL2.
This delay in driving the read bit lines leads to the delay in a timing for driving the SA, which directly results in an increase in the access time.
Note here that the data read out onto the write bit lines WBL2 and /WBL2 in this operation are not used at all, but behave just like pseudo read data (PRD).
Meanwhile, in the memory cell 1a, the write data WD and /WD written by the write access transistor 2 are transferred also to the read bit lines RBL1 and /RBL1 through the read access transistor 3. However, the delay in the write operation does not result from the read bit lines RBL1 and /RBL1, because a write amplifier for driving the write bit lines WBL1 and /WBL1 has a high current-carrying capability.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor memory having ports, each of which conducts exclusively a writing or reading operation, by which the access operation can be speeded up when cells at the same row address are accessed simultaneously through two ports.
The present invention accomplishes the above-stated object by differentiating the access capabilities between the reading operation and the writing operation.
To begin with, the present inventors take note of operating margins in the reading operation and the writing operation. In general, during the writing operation, on inputting data to be written from the outside, address systems can be operated concurrently, and therefore there is a margin of the timing comparatively, and the operation time is not limited by external specifications. Generally speaking, there are no specifications on the writing time. Insofar as the writing operation has been finished within a cycle, the delay in the writing operation is not a problem. Compared with the writing operation, the reading operation is stipulated by the external specifications as an access time that is the most important specification in a memory circuit. Therefore, the reading operation should be conducted on a top-priority basis. In view of these characteristics, the writing operation is intentionally delayed within a range capable of finishing the operation, while a high priority is assigned to the reading operation, whereby the reading operation can be speeded up.
That is to say, between the write access path and the read access path, which are designed equally in the conventional technique, the access time for the write path is delayed relative to that for the read path. Thereby, a load capacitance of the write bit lines is reduced, when considered from the standpoint of the memory cells. As a result, a driving capability for the read bit lines can be increased corresponding to the reduced amount.
More specifically, the following measures may be employed to fulfill the object, where access transistors made up of NMOS transistors are modified in such a manner that:
a gate width of write access transistors is made smaller than that on the reading side;
a gate length of write access transistors is made longer than that on the reading side;
a thickness of a gate oxide film of write access transistors is made larger than that on the reading side;
an ON-state voltage (Vgs) of gates of write access transistors is made smaller than that on the reading side;
a substrate voltage (Vbs) of write access transistors is made smaller than that on the reading side; and
a threshold voltage of write access transistors is made higher than that on the reading side
In addition, a method for fulfilling the object without modifying the access transistors includes a resistance component of the write path being made larger than that on the reading side.